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ASAHI KASEI
[AKD4631-VN]
AKD4631-VN
AK4631-VN Evaluation board Rev.1
GENERAL DESCRIPTION AKD4631-VN is an evaluation board for the AK4631VN, 16bit mono CODEC with MIC/SPK amplifier. The AKD4631-VN can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). AKD4631-VN also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4631-VN --- Evaluation board for AK4631VN (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * BNC connector for an external clock input * 10pin Header for serial control mode
AVDD DVDD SVDD 3.3V Regulator GND
5V
MIC-Jack MIC
Control Data 10pin Header
BEEP/MIN/MOUT AOUT SPK-Jack
DSP
AK4631VN
10pin Header
AK4114
Opt In Opt Out
Clock Gen
Figure 1. AKD4631-VN Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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[AKD4631-VN]
Evaluation Board Manual Operation sequence
1) Set up the power supply lines. 1-1) When AVDD, DVDD, SVDD, and VCC are supplied from the regulator. (AVDD, DVDD, SVDD, and VCC jack should be open.). See "Other jumper pins set up (page 10)". [REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [AGND] [DGND] (red ) (orange) (orange) (blue) (orenge) (black) (black) (black) = 5V = open = open = open = open = 0V = 0V = 0V
: 3.3V is supplied to AVDD of AK4631-VN from regulator. : 3.3V is supplied to DVDD of AK4631-VN from regulator. : 3.3V is supplied to SVDD of AK4631-VN from regulator. : 3.3V is supplied to logic block from regulator. : for analog ground : for analog ground : for logic ground
1-2) When AVDD, DVDD, SVDD, and VCC are not supplied from the regulator. (AVDD, DVDD, SVDD, and VCC jack should be junction.) See "Other jumper pins set up (page 10)". [REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [AGND] [DGND] (red) (orange) (orange) (blue) (orenge) (black) (black) (black) = "REG" jack should be open. = 2.6 3.6V : for AVDD of AK4631-VN (typ. 3.3V) = 2.6 3.6V : for DVDD of AK4631-VN (typ. 3.3V) = 2.6 5.25V : for SVDD of AK4631-VN (typ. 3.3V, 5.0V) = 2.6 3.6V : for logic (typ. 3.3V) = 0V : for analog ground = 0V : for analog ground = 0V : for logic ground
Each supply line should be distributed from the power supply unit. AVDD and DVDD must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4631VN and AK4114 should be reset once bringing SW1, 2 "L" upon power-up.
Evaluation mode
In case of AK4631VN evaluation using AK4114, it is necessary to correspond to audio interface format for AK4631VN and AK4114. About AK4631VN's audio interface format, refer to datasheet of AK4631VN. About AK4114's audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of loop-back mode (A/D D/A) : PLL, Master Mode (Default) (2) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) (3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) (4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode (5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
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[AKD4631-VN]
(1) Evaluation of loop-back mode (A/D D/A) : PLL, Master Mode (Default) a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4631-VN should be set to "0". X'tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X2. X'tal of 11.2896MHz (Default) is set on the AKD4631-VN. Set "No.8 of SW3" to "H". When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6 MCKI JP17 XTE JP18 MKFS
JP21 MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock Output frequency (16fs/32fs/64fs) of BICK should be set by "BCKO1-0 bit" in the AK4631-VN. There is no necessity for set up JP19.
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP22 FCK_SEL
JP28 FCK
DIR 2fs 1fs EXT
ADC
d) Set up jumper pins of DATA When the AK4631VN is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI JP26 4631_SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4631-VN]
(2) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4631VN should be set to "0". X'tal of 11.2896MHz (Default) is set on the AKD4631-VN. In this case, the AK4631VN corresponds to PLL reference clock of 12.2896MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4631VN is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then "MCKO bit" in the AK4631VN should be set to "1". When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to match the output impedance of the clock generator.
JP17 XTE JP18 MKFS
JP6 MCKI
JP21 MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP22 FCK_SEL
JP28 FCK
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When the AK4631-VN is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI JP26 4631_SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4631-VN]
(3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4631VN should be set to "1". JP6 (MCKI) should be open. b) Set up jumper pins of BICK clock When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to match the output impedance of the clock generator.
JP17 XTE
JP21 MCLK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
XTL DIR EXT
INV
THR
DIR ADC
INV
THR
In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn "256fs", "512fs", "1024fs" from left.
JP18 MKFS
JP18 MKFS
JP18 MKFS
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
And input frequency of BICK is set up in turn "16fs", "32fs", "64fs" from left.
JP19 BICK_SEL
JP19 BICK_SEL
JP19 BICK_SEL
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
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[AKD4631-VN]
c) Set up jumper pins of FCK clock When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP22 FCK_SEL
JP28 FCK
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When the AK4631VN is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI
JP26 4631_SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4631-VN]
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4631VN should be set to "0".
JP6 MCKI
JP17 XTE
JP21 MCLK_SEL
JP18 MKFS
XTL DIR EXT
256fs 512fs 1024fs
b) Set up jumper pins of BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP28 FCK
JP22 FCK_SEL
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When D/A converter of the AK4631-VN is evaluated by using DIR of AK4114, the jumper pins should be set to the following.
JP30 SDTI
JP26 4631_SDTI
DIR
ADC
DAC/LOOP ADC
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ASAHI KASEI
[AKD4631-VN]
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4631-VN should be set to "0".
JP6 MCKI
JP17 XTE
JP21 MCLK_SEL
JP18 MKFS
XTL DIR EXT
256fs 512fs 1024fs
b) Set up jumper pins of BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP28 FCK
JP22 FCK_SEL
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When A/D converter of the AK4631-VN is evaluated by using DIR of AK4114, the jumper pins should be set to the following.
JP30 SDTI
JP26 4631_SDTI
DIR
ADC
DAC/LOOP ADC
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ASAHI KASEI
[AKD4631-VN]
DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4631-VN and AK4114 ON is "H", OFF is "L". No. Name ON ("H") OFF ("L") 1 DIF0 AK4114 Audio Format Setting 2 DIF1 See Table 2 3 CM2 Clock Operation Mode select 4 CM0 See Table 3 5 CM1 6 OCKS0 Master Clock Frequency Select See Table 4 7 OCKS1 8 M/S Master mode Slave mode Note. When the AK4631-VN is evaluated Master mode, "No.8 of SW3" is set to "H". Table 1. Mode Setting for AK4631-VN and AK4114
Resistor setting for AK4631-VN Audio Interface Format
Setting for AK4114 Audio Interface Format
DIF1 bit 0 1 1
DIF0 bit 1 0 1
DIF0 L L H
DIF1 L L L
DIF2 L H H
DAUX 24bit, Left justified 24bit, Left justified 24bit, I S
2
SDTO 16bit, Right justified 24bit, Left justified 24bit, I S
2
Default
Note. When the AK4631-VN is evaluated by using DIR/DIT of AK4114, "No.8 of SW3" is set to "L". Table 2. Setting for AK4114 Audio Interface Format UNLOCK PLL X'tal Clock source SDTO ON ON(Note) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 2 1 0 Default 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-down) Note : When the X'tal is not used as clock comparison for fs detection (i.e. XTL1,0= "1,1"), the X'tal is off. Default setting is recommended. Table 3. Clock Operation Mode select No. 0 2 OCKS1 0 1 MCKO1 256fs 512fs MCKO2 256fs 256fs X'tal 256fs 512fs Mode 0 1 CM1 0 0 CM0 0 1
Default
Table 4. Master Clock Frequency Select (Stereo mode)
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[AKD4631-VN]
Other jumper pins set up
1. JP1 (GND) OPEN SHORT 2. JP2 (AIN) OPEN SHORT : Analog ground and Digital ground : Separated. : Common. (The connector "DGND" can be open.) : Connection between MICOUT pin and AIN pin of the AK4631VN. : No connection. : Connection.
3. JP3 (AVDD_SEL) : AVDD of the AK4631VN REG : AVDD is supplied from the regulator ("AVDD" jack should be open). < Default > AVDD : AVDD is supplied from "AVDD " jack. 4. JP9 (DVDD_SEL) : DVDD of the AK4631VN AVDD : DVDD is supplied from "AVDD". < Default > DVDD : DVDD is supplied from "DVDD " jack. 5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line. DVDD : Logic block of LVC is supplied from "DVDD". < Default > VCC : Logic block of LVC is supplied from "VCC " jack. 6. JP11 (VCC_SEL) : Logic block is selected supply line. LVC : Logic is supplied from supply line of LVC. < Default > VCC : Logic block of LVC is supplied from "VCC " jack. 7. JP4 (SVDD_SEL) : SVDD of the AK4631VN REG : SVDD is supplied from the regulator ("SVDD" jack should be open). < Default > SVDD : SVDD is supplied from "SVDD " jack. 8. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114. MCKO1 : The check from MCKO1 of AK4114 is provided to MCKI of the AK4631VN. < Default > MCKO2 : The check from MCKO2 of AK4114 is provided to MCKI of the AK4631VN.
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ASAHI KASEI
[AKD4631-VN]
The function of the toggle SW
[SW1] (DIR) : Power control of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used. : Power control of AK4631VN. Keep "H" during normal operation.
[SW2] (PDN)
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4631-VN can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10 wire flat cable packed with the AKD4631-VN
Connect PC
CSN CCLK AKD4631-VN CDTI
10 wire flat cable
10pin Connector
10pin Header
Figure 2. Connect of 10 wire flat cable
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[AKD4631-VN]
Analog Input / Output Circuits
(1) Input Circuits a) MIC Input Circuit
J1 MIC-JACK
6 4 3
AVSS J3 MIC
JACK RCA
JP12 MIC_SEL INT
2 3 1
MR-552LS AVSS
Figure 3. MIC Input Circuit (a-1) Analog signal is input to MIC pin via J1 connector.
JP12 MIC_SEL
RCA JACK
(a-2) Analog signal is input to MIC pin via J3 connector.
JP12 MIC_SEL
RCA JACK
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[AKD4631-VN]
(2) Output Circuits a) AOUT Output Circuit
C28 AOUT
1
+
2
R20 220
1u
R21 20k AVSS
2 3 1
J5 AOUT
MR-552LS
AVSS
Figure 4. AOUT Output Circuit
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[AKD4631-VN]
b) SPK Output Circuit Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14 (SPN_SEL) should be open, or "PMSPK bit" in the AK4631-VN should be set to "0".
JP31 Dynamic J2 SPK-JACK
R15 10 SPP JP13
K
SVSS
3 4 6
D1
A
Dynamic(EXT) Piezo(EXT) Dynamic CN5 Dynamic(EXT) Piezo(EXT) Dynamic
2
SPK1 020S16 R
SVSS
DIODE ZENER D2
A K
SPP_SEL JP14
SVSS
DIODE ZENER
SPN_SEL
1
R17 10 SPN
L
Figure 5. SPK Output Circuit (b-1) An external dynamic speaker is evaluated by using J2 (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
(b-2) An external Piezo speaker is evaluated by using J2 (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
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[AKD4631-VN]
(b-3) Analog signal of SPP/SPN pins are output from "Dynamic Speaker" on the evaluation (SPK1).
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
(3) BEEP/MIN/MOUT Input and Output Circuit
C24 1u +
2
1
J4 BEEP/MIN/MOUT 2 3 1 MR-552LS AVSS
JP15 MIN/MOUT
MOUT C25 0.1u
OUT IN
R16 20k AVSS
2
C26 1u +
JP16
1
MOUT MIN BEEP
MIN R19 BEEP 20k
R18 47k AVSS
BEEP/MIN/MOUT
Figure 6. BEEP/MIN/MOUT Input and Output Circuit (3-1) Analog signal is input to MIN pin from J4 connector. JP15 JP16 BEEP/MIN/MOUT MIN/MOUT
MOUT MIN BEEP
IN
OUT
(3-2) Analog signal of MOUT pin is output from J4 connector.
JP15 MIN/MOUT JP16 BEEP/MIN/MOUT MOUT MIN BEEP
IN
OUT
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ASAHI KASEI
[AKD4631-VN]
(3-3) Analog signal of MOUT pin is input to MIN pin. JP15 JP16 BEEP/MIN/MOUT MIN/MOUT
MOUT MIN BEEP
IN
OUT
(3-4) Analog signal is input to BEEP pin from J4 connector. JP15 JP16 BEEP/MIN/MOUT MIN/MOUT
MOUT MIN BEEP
IN
OUT
AKM assumes no responsibility for the trouble when using the above circuit examples.
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ASAHI KASEI
[AKD4631-VN]
2. Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4631-VN according to previous term. 2. Connect IBM-AT compatible PC with AKD4631-VN by 10-line type flat cable (packed with AKD4631-VN). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK4631VN Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "akd4631.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button.
Explanation of each buttons
1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4631VN. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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[AKD4631-VN]
Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4631VN, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4631VN, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL
Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4631VN by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4642, click [OK] button. If not, click [Cancel] button.
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[AKD4631-VN]
4. [Save] and [Open] 4-1. [Save]
Save the current register setting data. The extension of file name is "akr".
(Operation flow)
(1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is "akr". 4-2. [Open] The register setting data saved by [Save] is written to AK4642. The file type is the same as [Save].
(Operation flow)
(1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.
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[AKD4631-VN]
5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is "aks".
Figure 1. Window of [F3]
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[AKD4631-VN]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure 2 opens.
Figure 2. [F4] window
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[AKD4631-VN]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 3.
Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed.
3-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
3-3. Note
(1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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[AKD4631-VN]
7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 5. (2) Click [WRITE] button, then the register setting is executed.
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[AKD4631-VN]
Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.
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[AKD4631-VN]
MEASUREMENT RESULTS EXAMPLE 1.AK4631 Mode: EXT mode (Slave)
[Measurement condition] * Measurement unit: ROHDE & SCHWARZ, UPD05 * MCKI: 256fs, 512fs * BICK: 64fs * Bit: 16bit * Sampling Frequency: 8kHz & 16kHz * Measurement Frequency: 20 3.4kHz (fs=8kHz), 20 8kHz (fs=16kHz) * Power Supply: AVDD=DVDD=3.3V,SVDD=3.3V/5.0V * Temperature: Room * Input Frequency: 1kHz [Measurement Results] 1.ADC characteristics (MIC Gain = +20dB, IPGA=0dB, ALC1 = OFF, MIC Result MCKI clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N 2. DAC characteristics (AOUT) (DAC MCKI clock Sampling Frequency S/(N+D) (0dBFS) D-Range (-60dBFS) S/N 3. Speaker-Amp characteristics (DAC S/(N+D) SVDD=3.3V RL=8 SVDD=5.0V RL=50 SVDD=3.3V RL=8 SVDD=5.0V RL=50 ADC DAC 512fs 8kHz 84.6dB 86.1dB 86.1dB 16kHz 84.1dB 85.0dB 85.0dB 8kHz 85.2dB 88.6dB 88.6dB 256fs 16kHz 84.1dB 84.9dB 85.0dB IPGA ADC)
AOUT, DVOL = 0dB) Result 512fs 8kHz 89.7dB 93.5dB 94.1dB MOUT 16kHz 89.0dB 91.1dB 92.2dB MIN 8kHz 86.0dB 93.7dB 94.5dB 256fs 16kHz 91.9dB 95.3dB 95.3dB
S/N
SPP/SPN, ALC2=OFF) Result SPKG1-0 = "00" (-0.5dBFS) 65.8dB SPKG1-0 = "01" (-0.5dBFS) 67.8dB SPKG1-0 = "10" (-0.5dBFS) 74.5dB SPKG1-0 = "11" (-0.5dBFS) 78.1dB SPKG1-0 = "00" 90.2dB SPKG1-0 = "01" 90.4dB SPKG1-0 = "10" 90.3dB SPKG1-0 = "11" 90.4dB
4. Loop-back (MIC
AOUT) Result
MCKI clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N
512fs 8kHz 84.4dB 85.9dB 86.0dB 16kHz 84.0dB 84.8dB 84.8dB 8kHz 84.7dB 87.8dB 87.9dB
256fs 16kHz 84.0dB 84.5dB 84.6dB
- 25 -
2005/12
ASAHI KASEI
[AKD4631-VN]
2.AK4631 Mode: PLL SLAVE mode
[Measurement condition] * Measurement unit: ROHDE & SCHWARZ, UPD05 * Bit: 16bit * Sampling Frequency: 8kHz & 16kHz * Measurement Frequency: 20 3.4kHz (fs=8kHz), 20 8kHz (fs=16kHz) * Power Supply: AVDD=DVDD=SVDD=3.3V * Temperature: Room * Input Frequency: 1kHz [Measurement Results] 2-1. PLL Reference clock : BICK or FCK pin Loop-back (MIC ADC DAC AOUT) Result PLL Reference clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N 1fs (FCK pin) 8kHz 16kHz 65.1dB 72.2dB 86.3dB 85.0dB 86.4dB 85.0dB 16fs (BICK pin) 8kHz 16kHz 85.0dB 83.6dB 87.8dB 85.0dB 87.9dB 85.0dB
2-2. PLL Reference clock : MCKI pin
Loop-back (MIC ADC DAC AOUT) Result 12.288MHz 8kHz 16kHz 84.5dB 83.4dB 86.3dB 85.1dB 86.6dB 85.2dB
PLL Reference clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N
3.AK4631 Mode: PLL MASTER mode
[Measurement condition] * Measurement unit: ROHDE & SCHWARZ, UPD05 * MCKI: 12.288 MHz * BICK: 16fs * Bit: 16bit * Sampling Frequency: 8kHz & 16kHz * Measurement Frequency: 20 3.4kHz (fs=8kHz), 20 8kHz (fs=16kHz) * Power Supply: AVDD=DVDD=SVDD=3.3V * Temperature: Room * Input Frequency:1kHz [Measurement Results] Loop-back (MIC ADC DAC AOUT) Result 8kHz 84.4dB 86.1dB 86.4dB
S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N
16kHz 83.9dB 85.3dB 85.3dB
- 26 -
2005/12
ASAHI KASEI
[AKD4631-VN]
4.PLOT DATA (EXT Slave mode) 4-1.ADC (MIC ADC) PLOT DATA
Figure 8. THD+N vs. Input Level
Figure 9. THD+N vs. Input Frequency (Input Level = -1dBFS) - 27 2005/12
ASAHI KASEI
[AKD4631-VN]
Figure 10. Linearity
Figure 11. Frequency Response
- 28 -
2005/12
ASAHI KASEI
[AKD4631-VN]
Figure 12. FFT Plot ( Input level=-1.0dBFS)
Figure 13. FFT Plot ( Input level=-60.0dBFS )
- 29 -
2005/12
ASAHI KASEI
[AKD4631-VN]
Figure 14. FFT Plot ( "0" data input )
- 30 -
2005/12
ASAHI KASEI
[AKD4631-VN]
4-2. DAC (DAC
AOUT) PLOT DATA
Figure 15. THD+N vs. Input Level
Figure 16. THD+N vs. Input Frequency (Input Level = 0dBFS) - 31 2005/12
ASAHI KASEI
[AKD4631-VN]
Figure 17. Linearity
Figure 18. Frequency Response
- 32 -
2005/12
ASAHI KASEI
[AKD4631-VN]
Figure 19. FFT Plot ( Input level=0dBFS )
Figure 20. FFT Plot ( Input level=-60.0dBFS )
- 33 -
2005/12
ASAHI KASEI
[AKD4631-VN]
Figure 21. FFT Plot ( "0" data input )
- 34 -
2005/12
ASAHI KASEI
[AKD4631-VN]
Revision History
Date 05/01/25 05/03/24 05/12/22 Manual Revision KM077300 KM077301 KM077302 Board Revision 0 0 1 Reason First Edition Revised Version up "Circuit diagram" Contents
Changed Control soft manual. USB I/F Board (AKDUSBIF-A) Ver. 3.0 "74HC541" of U11 (5 of 5) was changed to "74LVC541".
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. - 35 2005/12
REG_IN T1 TA48033F
GND IN OUT 1
JP1 GND AVSS REG C2 0.1u C3 + 47u AVSS SVSS CN1 32pin_4
32 31 30 29 28 27 26 25
INT
MOUT
AOUT
A
B
C
D
E
BEEP
REG T45_R
1
AVDD T45_O
1
DVDD T45_O
1
AVSS T45_BK
1
SVDD T45_BU
1
SVSS T45_BK
1
DGND T45_BK
E
E
C1 0.1u
2
TP27 TP26 TP25 BEEPAOUT MOUT
1 1 1
AVSS R1 2.2k + C6 1u C7 0.22u
REG_IN
AVDD
DVDD
AVSS
SVDD
SVSS
TP31 TP30 TP29 MPI MIC MICOUT
1 1 1
JP2 AIN TP28 AIN
1
D
1
D
TP32 VCOM
28 27 26 24 25 23 22
CN2 AVDD_IN L1
1 1 2
BEEP
MIC
AIN
MICOUT
AOUT
REG
JP3 AVDD_SEL AVDD
1 2
1
TP3 AVSS
1
MOUT
MPI
AVSS
C4 2.2u
+
C5 0.1u C10 0.1u
1
REG
U1
TP24 MIN REG
1
C9 10u
CN3
MIN SVSS SVDD 21 1
C13 47u
C
+
2
(short)
AVDD AVSS
3 4 5 6 7
TP2 AVDD R2 C8 4.7n AVSS 10k
1
TP1 VCOC
3 4 5 6 7
AVDD VCOC PDN CSN CCLK DVDD SDTO DVSS BICK CDTI SDTI FCK
19 18 17 16 15
C11 0.1u R3 (short)
1
AK4631VN
SPN SPP MCKO MCKI
AVSS
TP20 SPN
1
1
R5 (short)
R4 (open)
1
21 20 19
SPN SPP 4631_MCKO 4631_MCKI SVSS
TP21 SPP TP19 MCKO
PDN
8
9
10
11
12
13
8
14
1
1
1
32pin_1
R6
51
18
TP8 PDN
JP6 MCKI MCKI TP18
17
AVSS 32pin_3
C20 0.1u
B
2
AVDD JP9 AVDD DVDD_SEL
2
TP9 CSN
1
TP10 TP11 CCLK CDTI
1 1
TP12 SDTI
1
TP13 TP14 SDTO FCK
1 1
TP15 BICK
1
+
DVDD_IN L4
1 1
R1410 DVDD
R7 51
R8 51
R9 51
R10 51
R11 51
R12 470
R13 470
1
C21 10u TP16 DVDD
AVSS
C22 47u
+
2
(short)
DVDD
R40 (short)
DVDD
JP10 LVC_SEL LVC
AVSS VCC(3.3V) L5
A
VCC LVC
2
JP11 VCC_SEL
10 11 12 13 14 15
1 1
D3.3V VCC
16
CN4 32pin_2
9
C23 47u
+
2
(short)
4631_SDTO
4631_BICK
4631_SDTI
4631_FCK
CSN
CCLK
DVDD
CDTI
A
B
C
+
+ +
1 2
VCOM AVSS
TP23 SVSS
SVSS TP22 SVDD
24 23 22
20
JP4 REG MIN SVDD_SEL SVSS SVDD 1
SVDD L2
2
C12 10u
(short)
C16 + 47u
C
B
A
Title Size Document Number
AKD4631-VN
AK4631-VN
Sheet
E
Rev
A3
Date:
D
1 1
of
Thursday, December 22, 2005
5
A
B
C
D
E
J1 MIC-JACK
6 4 3
JP31 Dynamic J2 SPK-JACK
3 4 6
E
AVSS J3 MIC
JACK RCA
JP12 MIC_SEL INT SPN
R15 10
SVSS
E
2 3 1
D1
A K
JP13
MR-552LS AVSS
2
Dynamic(EXT) Piezo(EXT) Dynamic CN5
2
SPK1 020S16 R
C24 1u
1
SVSS MOUT C25 0.1u SVSS
DIODE ZENER D2
A K
SPN_SEL JP14 Dynamic(EXT) Piezo(EXT) Dynamic
J4 BEEP/MIN/MOUT 2 3 1 MR-552LS
D
JP15 MIN/MOUT
+
OUT IN
R16 20k AVSS
DIODE ZENER
SPP_SEL
1
AVSS C26 1u
2 1
R17 10 JP16 MOUT MIN BEEP BEEP/MIN/MOUT 20k SPP MIN R19 BEEP
L
D
+ + R18 47k AVSS
C28 + AOUT
1 2
R20 220
1u
R21 20k AVSS
2 3 1
J5 AOUT
MR-552LS
C
C
AVSS
B
B
A
A
Title Size Document Number
AKD4631-VN
Input/Output
Sheet
E
Rev
A3
Date:
A B C D
1 2
of
Thursday, December 22, 2005
5
A
B
C
D
E
for 74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
D3.3V 12.288MHz X1
1 2
E
C30 0.1u
C31 0.1u
C32 0.1u
C33 0.1u
C34 0.1u
C35 0.1u
C36 0.1u
1
+ C37 47u
E
R24 1M
U2A
1 2 3
U2B
4
74HCU04 JP17 XTE C38 5p C39 5p
74HCU04
D
2
D
EXT_MCLK
VCC
VCC JP18 MKFS
10 11
10
4
U4A 74AC74
Q 5 12 11 D CLK
U4B 74AC74
Q 9
PR
DIR_MCLK
C
XTL DIR EXT
JP21
R25 short
D CLK
PR
2 3
256fs 512fs 1024fs MCKO
U3
CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
64fs 32fs 16fs EXT
JP19 BICK_SEL
THR
1 2
JP20 BICK EXT_BICK
CL
Q
6
CL
Q
8
MCLK_SEL
13
U5A 74HC14 JP22
INV
C
1
74VHC4040 MCKO
2fs 1fs EXT
EXT_FCK FCK_SEL
J8 EXT/BICK
B
2 3 1
MR-552LS AVSS
R26 51 JP23 EXT1
B
J9 FCK
2 3 1
MR-552LS AVSS
A
R27 51 JP24 EXT2
Title Size Document Number
A
AKD4631-VN
CLOCK
Sheet
E
Rev
A3
Date:
A B C D
1 3
of
Thursday, December 22, 2005
5
A
B
C
D
E
C40 C41 0.1u 0.1u D3.3V
1
D3.3V L6 (short)
E
R28 10k U5B
4 3 6
K
PORT1
VCC GND OUT 3 2 1
C42 0.1u R29 470 C43 10u
2 1
U5C
5
3
C45 0.1u
C44 0.1u
2
1
TORX141
D3.3V
74HC14
74HC14
L
A
D3 HSU119
E
2
H SW1 DIR
+
C46 0.47u
R30 18k
45
41
39
47
43
48
46
44
D
DIF0 DIF1 DIF2 CM0 CM1 OCKS0 OCKS1 M/S
SW3
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
U6
42
VCOM
AVSS
40
R
TEST1
AVDD
NC
RX3
RX2
RX1
NC
RX0
38
INT1
37
D
U7A
INT0 36 1 2
R31 1k
K
LED1 ERF
A
1
IPS0
D3.3V
74HC04
2 NC OCKS0 35
OCKS0
RP1
9 8 7 6 5 4 3 2 1 3 DIF0 OCKS1 34
OCKS1
CM0 CM1 OCKS0 OCKS1 M/S
4
TEST2
CM1
33
CM1
5
DIF1
CM0
32
CM0
C
47k
C
6
NC
1
7
DIF2
AK4114
PDN
31
C47 5p
XTI 30
X2 11.2896MHz
IPS1 XTO 2 8 29
C48 5p
9
P/SN
DAUX
28
DAUX
10
XTL0
MCKO2
27
11
B
XTL1
BICK
26
DIR_BICK
B
12
VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
SDTO
25
DIR_SDTI
13
14
15
16
17
18
19
20
21
22
23
C49 0.1u +
C50 0.1u +
24
DIR_FCK
JP25 MCKO_SEL MCKO2 MCKO1 DIR_MCLK
1
2
1
2
C51 10u D3.3V PORT2
A
C52 10u D3.3V
A
IN VCC GND
3 2 1
D3.3V C53 0.1u
Title Size Document Number
TOTX141
AKD4631-VN
DIR/DIT
Sheet
E
Rev
A3
Date:
A B C D
1 4
of
Thursday, December 22, 2005
5
A
B
C
D
E
U9
E
U8
LVC
20
1 11 Y8 A8 9
DIR
VCC
E
M/S
19 G GND 10
C54 0.1u
MCKO
12
Y7
A7
8
4631_MCKO RP2 RP3
7 6 5 4 3 2 1 2 A1 B1 18 7 6 5 4 3 2 1
4631_MCKI
13
Y6
A6
7
EXT_MCLK
3
DAUX
14
Y5
A5
6
4631_SDTO JP26 4631_SDTI DAC/LOOP 47k
A2
B2
17
4
4631_SDTI
15
Y4
A4
5 5
A3
B3
16
47k
16
D
Y3
A3
4
ADC
6
A4
B4
15
D
17
Y2
A2
3 7
A5
B5
14
18
Y1
A1
2 8
A6
B6
13
JP27 BICK
12
ADC DIR
EXT_BICK DIR_BICK
10
GND
G2
19
4631_BICK
A7
B7
C55 0.1u
20 VCC G1 1
4631_FCK
9
A8
B8
11
JP28 FCK
ADC DIR
EXT_FCK DIR_FCK
74LVC541
74LVC245
C
C
LVC + C56 47u
1
U10A
2
JP29 INV THR BICK_INV
2
1
74HC14
D3V
R32 R34 R36
10k 10k 10k
R33 R35 R37
470 470 470
U11
2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 VCC GND 18 17 16 15 14 13 12 11 20 10
CSN CCLK CDTI PDN
4631_MCKI MCLK BICK FCK SDTI VCC
1 2 3 4 5
PORT3
10 9 8 7 6
PORT4
1 2 3 4 5 10 9 8 7 6
CSN CCLK CDTI
B
D3V R38
ROM
B
CTRL
74LVC541
D3V 10k ADC
D3V
K
DAUX
A
D4 HSU119
R39 10k U5D
9 8 11
JP30 SDTI DIR
10
DIR_SDTI
U5E 74HC14 U2C
5 6 13
L
3 1
H SW2 PDN
2
74HC14
U2F
12 9
U7D
8 3
U10B
4
74HCU04 C57 0.1u U2D
9 8 3
74HCU04 U7B
4 11
74HC04 U7E
10 5
74HC14 U10C
6 11
U10E
10
A
A
74HCU04 U2E
11 10 5
74HC04 U7C
6 13
74HC04 U7F
12 9
74HC14 U10D
8 13
74HC14 U10F
12 Title Size Document Number
74HCU04
74HC04
74HC04
74HC14
74HC14
AKD4631-VN
LOGIC
Sheet
E
Rev
A3
Date:
A B C D
1 5
of
Thursday, December 22, 2005
5

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